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September 14, 2019
Analog Design Using Cadence
By Er.Jada Harshil, Silicon Design Engineer, AMD Hyderabad
In this workshop everyone will be capable of designing analog circuits using cadence by providing hands-on training on the state-of-the-art Cadence EDA tools for VLSI Design. The participants will have an exposure to the Circuit Design & Simulation, Layout, Physical Verification (DRC, LVS), and Extraction. The workshop includes practice sessions on the Cadence design and simulation tools (Encounter, RTL Compiler, Virtuoso, Spectre, Assura and Incisive).
Mr. Jada Harshil is currently working as silicon design engineer at AMD, Hyderabad. He has an experience of working as a research associate under SMDP project at NIT, Kurukshetra. He has completed his Post graduation from NIT, Kurukshetra and graduation from JNTU, Hyderabad. He is having a vast industry experience in designing analog and digital circuits using cad tools.
- WHERE: Seminar Hall, Block-A
- WHEN: Saturday, 14th September 2019
- ADMISSION: Open to the Public
- TAGS: Layout, Physical Verification, Front end and back end
- AUDIENCE: Students