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September 7, 2019
Power Minimization in VLSI Circuits
By Dr. Sunil Jadev, Assistant Professor, JCBU Haryana
This presentation will give clear explanation on continued scaling of the CMOS technology that has led us into the deep submicron regimes where design is not limited by the functionality on a chip but is constrained with its power consumption. We will be presenting some widely used techniques for static and dynamic power minimization in modern VLSI circuits. These techniques are applicable on the different stages of the system design, starting from technology level where designer is allowed to change technology parameters (transistor sizes, supply and threshold voltages) up to the top level which deals with the design’s architectural variations. With this lecture the audience will be enhanced with designing capability in the field of power consumption.
Dr. Sunil Jadav is currently working as Assistant Professor in the department of ECE in JC Bose University of Science and Technology, YMCA, Faridabad, Haryana. He has published more than 30 research papers in peer reviewed international / national journals and conferences. His area of research includes communication and semiconductor technology (Digital & Analog IC Design).
- WHERE: Seminar Hall, Block-A
- WHEN: Saturday, 07th September 2019
- ADMISSION: Open to the Public
- TAGS: CMOS Technology, Placement and Routing Technology
- AUDIENCE: Students