Description:- This presentation will give a clear explanation which continued scaling of the CMOS technology that has led us into the deep submicron regimes where design is not limited by the functionality on a chip but is constrained with its power consumption. we present some widely used techniques for static and dynamic power minimization in modern VLSI circuits. These techniques are applicable on the different stages of the system design, starting from technology level where designer is allowed to change technology parameters (transistor sizes, supply and threshold voltages) up to the top level which deals with the design’s architectural variations. with this lecture, the audience is enhanced with designing capability in the field of power consumption.
Bio-Profile: Dr. G.Dhanalakshmi Ph.D. (Vlsi Design), M. Tech (Vlsi Design), B. Tech (ECE), his field of interest in VLSI design & Robotics and Published papers in National and International journals.
Admission: Registration required
Audience: ECE Students
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