Workshop on “Analog Design Using Cadence”

In this workshop, everyone will be capable of designing analog circuits using cadence by providing hands-on training on state-of-the-art Cadence EDA tools for VLSI Design. The participants will have exposure to the Circuit Design & Simulation, Layout, Physical Verification (DRC, LVS), and Extraction. The workshop includes practice sessions on the Cadence design and simulation tools (Encounter, RTL Compiler, Virtuoso, Spectre, Assura, and Incisive)

Speaker-Bio:

Mr. Jada Harshil is currently working as silicon design engineer at AMD, Hyderabad. He has an experience of working as a research associate under SMDP project at NIT, Kurukshetra. He has completed his Post graduation from NIT, Kurukshetra and graduation from JNTU, Hyderabad. He is having a vast industry experience in designing analog and digital circuits using cad tools.

Start Time

8:00 am

September 14, 2019

Finish Time

6:00 pm

September 14, 2019

Address

SEMINAR HALL, BLOCK-A