Event Description:- In this workshop all will be capable of designing analog circuits using cadence by providing hands-on training on the state-of-the-art Cadence EDA tools for VLSI Design. The participants will have an exposure to the Circuit Design & Simulation, Layout, Physical Verification (DRC, LVS), and Extraction. The workshop includes practice sessions on the Cadence design and simulation tools (Encounter, RTL Compiler, Virtuoso, Spectre, Assura and Incisive).

Bio-Profile: Dr. Shubham Tayal Ph.D (Microelectronics & Vlsi Design), M. Tech (Vlsi Design), B. Tech (ECE), his field of intrerest in VLSI design and Published papers in National and International journals.

Admission: Registration required

Audience: ECE & EEE Students

Contact: events@ashoka.ac.in, 6300197819

More Info: for more details, Log on to www.ashoka.ac.in